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  1/12 september 2001 n high speed : t pd = 26ns (typ.) at v cc = 4.5v n low power dissipation: i cc =4 m a(max.) at t a =25c n compatible with ttl outputs : v ih = 2v (min.) v il = 0.8v (max) n symmetrical output impedance: |i oh | = i ol = 4ma (min) n balanced propagation delays: t plh @ t phl n pin and function compatible with 74 series 165 description the m74hct165 is an high speed cmos 8 bit piso shift register fabricated with silicon gate c 2 mos technology. this device contains eight clocked master slave rs flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. parallel data enters when the shift/load input is low. the parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. for clocked operation, shift/load must be high. the two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate. to avoid double clocking, however, the inhibit signal should only go high while the clock is high. otherwise the rising inhibit signal will cause the same response as rising clock edge. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hct165 8 bit piso shift register pin connection and iec logic symbols order codes package tube t & r dip M74HCT165B1R sop m74hct165m1r m74hct165rm13tr tssop m74hct165ttr tssop dip sop
m74hct165 2/12 input and output equivalent circuit pin description truth table a........h : the level of steady input voltage at inputs a through respectively qan - qgn : the level of qa - qg, respectively. before the most-recent transition of the clock logic diagram pin no symbol name and function 1 shift/load data inputs 2 qh complementary output 7 qh serial output 9 clock clock input (low to high, edge triggered 10 si serial data inputs 11, 12, 13, 14, 3, 4, 5, 6 a to h parallel data inputs 15 clock inh clock inhibit 8 gnd ground (0v) 16 vcc positive supply voltage inputs internal outputs outputs shift / load clock inh clock si a..........h qa qb qh l x x x a..........h a b h h l h x h qan qgn h l l x l qan qgn h l h x h qan qgn h l l x l qan qgn hxhxx no change h h x x x no change
m74hct165 3/12 timing chart absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 c to 85 c symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 50 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c
m74hct165 4/12 recommended operating conditions dc specifications symbol parameter value unit v cc supply voltage 4.5 to 5.5 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r , t f input rise and fall time (v cc = 4.5 to 5.5v) 0 to 500 ns symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 4.5 to 5.5 2.0 2.0 2.0 v v il low level input voltage 4.5 to 5.5 0.8 0.8 0.8 v v oh high level output voltage 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 v i o =-4.0 ma 4.18 4.31 4.13 4.10 v ol low level output voltage 4.5 i o =20 m a 0.0 0.1 0.1 0.1 v i o =4.0 ma 0.17 0.26 0.33 0.40 i i input leakage current 5.5 v i = v cc or gnd 0.1 1 1 m a i cc quiescent supply current 5.5 v i = v cc or gnd 44080 m a d i cc additional worst case supply current 5.5 per input pin v i = 0.5v or v i = 2.4v other inputs at v cc or gnd i o = 0 2.0 2.9 3.0 ma
m74hct165 5/12 ac electrical characteristics (c l = 50 pf, input t r = t f = 6ns) capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t tlh t thl output transition time 4.5 8151922ns t plh t phl propagation delay time (clock - qh, q h) 4.5 24 37 46 56 ns t plh t phl propagation delay time (clock inh - qh, qh ) 4.5 24 37 46 56 ns t plh t phl propagation delay time (shift/load - qh, q h) 4.5 26 40 50 60 ns t plh t phl propagation delay time (h - qh, q h) 4.5 22 34 43 51 ns f max maximum clock frequency 4.5 30 46 24 mhz t w(h) t w(l) minimum pulse width (clock) 4.5 8151922ns t w(l) minimum pulse width (shift/load ) 4.5 8151922ns t s minimum set-up time (pi - shift/load ) 4.5 7151922ns t s minimum set-up time (shift/load - ck, chinh) 4.5 7151922ns t s minimum set-up time (si - ck, chinh ) 4.5 7151922ns t h minimum hold time(pi - shift/ load ) (shift/ load -ck, chinh) 4.5 0 0 0 ns t rem minimum removal time (clock - ck inh) 4.5 5151922ns symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5101010pf c pd power dissipation capacitance (note 1) 96 pf
m74hct165 6/12 test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r t = z out of pulse generator (typically 50 w ) waveform 1 : serial mode propagation delay (f=1mhz; 50% duty cycle)
m74hct165 7/12 waveform 2 : parallel mode propagation delay (f=1mhz; 50% duty cycle) waveform 3 : minimum pulse width (s/l ), propagation delay times (f=1mhz; 50% duty cycle)
m74hct165 8/12 waveform 4 : setup and hold time (pi to s/l ) (f=1mhz; 50% duty cycle) waveform 5 : minimum removal time (ck inh to ck) (f=1mhz; 50% duty cycle)
m74hct165 9/12 dim. mm. inch min. typ max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 plastic dip-16 (0.25) mechanical data p001c
m74hct165 10/12 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data po13h
m74hct165 11/12 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop16 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080338d
m74hct165 12/12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com


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